library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.std_logic_unsigned.all;
--use ieee.numeric_std.all;

entity CompAD9826 is 
port (
      GReset     : IN STD_LOGIC;
      SYSCLK:         in STD_LOGIC;
		ClkADCprog   : IN STD_LOGIC;
		SyncInput : IN STD_LOGIC;
      SW:             in STD_LOGIC_VECTOR(7 downto 0);
      ADC_D:          inout STD_LOGIC_VECTOR(15 downto 0);
      XFER1_N:            inout STD_LOGIC;
      OUFLOW1:        inout STD_LOGIC;
      -- OUTEN_N:        out STD_LOGIC;
      DataIn:         IN STD_LOGIC_VECTOR(7 downto 0);
      ADCCLK:         out STD_LOGIC;
      CDSCLK1:        out STD_LOGIC;
      CDSCLK2:        out STD_LOGIC;
      SCLK:           inout STD_LOGIC;
      SLOAD_N:        inout STD_LOGIC;
      SDATA:          inout STD_LOGIC;
      JP5IN:          inout STD_LOGIC_VECTOR(5 downto 1); -- note not on old board
      DEBUG1:         inout STD_LOGIC
     );
end CompAD9826;
architecture ArchAD9826 of CompAD9826 is
-- multiplier 
 signal mult_out:        std_logic_vector(18 downto 0);
 signal ADC_Dres         : STD_LOGIC_VECTOR(15 downto 0);
 signal D_latch:         std_logic_vector(18 downto 0);
 signal Dl:              std_logic_vector(18 downto 0);
 signal sample_weight:   std_logic_vector(2 downto 0);
 signal addsub_out:      std_logic_vector(18 downto 0);
 signal add_sub:         std_logic;
 signal cin:             std_logic;
 signal accumulator:     std_logic_vector(18 downto 0);
 signal ped_done:        std_logic;
 signal valid:           std_logic;
 signal cds_done:        std_logic;

component CompAD9826control
port (
      GReset       : IN  STD_LOGIC;  
      SYSCLK:         in STD_LOGIC;
		ClkADCprog   : IN STD_LOGIC;
		SyncInput : IN STD_LOGIC;
      SW:             in STD_LOGIC_VECTOR(7 downto 0);
      ADC_Dres     : OUT STD_LOGIC_VECTOR(15 downto 0);
      XFER1_N:            inout STD_LOGIC;
      OUFLOW1:        inout STD_LOGIC;
  --      OUTEN_N:        out STD_LOGIC;
      DataIn:         IN STD_LOGIC_VECTOR(7 downto 0);
      ADCCLK:         out STD_LOGIC;
      CDSCLK1:        out STD_LOGIC;
      CDSCLK2:        out STD_LOGIC;
      SCLK:           inout STD_LOGIC;
      SLOAD_N:            inout STD_LOGIC;
      SDATA:          inout STD_LOGIC;
      JP5IN:              inout STD_LOGIC_VECTOR(5 downto 1); -- note not on old board
      DEBUG1:         inout STD_LOGIC;--
      Dl:             out std_logic_vector(18 downto 0);--(18 downto 0);
      D_latch:        out std_logic_vector(18 downto 0);
  --      sample_weight:  out std_logic_vector(2 downto 0);
      ped_done:       out std_logic;
      cds_done:       out std_logic;
      accumulator:    out std_logic_vector(18 downto 0);
      addsub_out:     in std_logic_vector(18 downto 0);
      add_sub:        out STD_LOGIC;
      valid:          out std_logic;
      cin:            out std_logic--;
  --      mult_out:       in std_logic_vector(18 downto 0)
     );
end component CompAD9826control;

component CompAD9826out
port (
      GReset:     in std_logic;
      SYSCLK:      in std_logic;
      ADC_D:       inout STD_LOGIC_VECTOR(15 downto 0);
      accumulator: in  std_logic_vector(18 downto 0);
      ped_done:    in std_logic;
      valid:       in std_logic;
      cds_done:    in std_logic
     );
end component CompAD9826out;

component CompAddSub
port
(
 add_sub	: IN STD_LOGIC ;
 cin		: IN STD_LOGIC ;
 dataa		: IN STD_LOGIC_VECTOR (18 DOWNTO 0);
 datab		: IN STD_LOGIC_VECTOR (18 DOWNTO 0);
 result		: OUT STD_LOGIC_VECTOR (18 DOWNTO 0)
);
end component CompAddSub;

begin
 -- include lpm package ( LPMpkg ) from the Cypress library 
 --U1: Mmult -- Configured as a multiplier (dataA * dataB) + 0
 --  generic map(
 --      lpm_widthA      => 16,
 --      lpm_widthB      => 2,--3,
 --      lpm_widthS      => 0,               -- optional
 --      lpm_widthP      => 19,--20,
 --      lpm_representation => lpm_unsigned, -- optional
 --      lpm_hint        => speed,           -- optional
 --      lpm_avalue      => ""               -- optional
 --  )
 --  port map(
 --      dataA           => D_latch(15 downto 0),
 --      dataB           => sample_weight(1 downto 0),--sample_weight(2 downto 0),
 --  --  sum             => ???,     -- optional
 --      result(18 downto 0)          => mult_out(18 downto 0)
 --  );
 -- include lpm package ( LPMpkg ) from the Cypress library 
 
 U2: CompAddSub    
 port map (
           add_sub         => add_sub,     -- optional
           cin             => cin,
           dataa           => D_latch(18 downto 0),  
           datab           => Dl(18 downto 0),
   --      clock           => SYSCLK,
           result          => addsub_out(18 downto 0)--addsub_out(18 downto 0) 
); 

U3: CompAD9826control
port map (
          GReset          => GReset,
          SYSCLK          => SYSCLK,
			 ClkADCprog   => ClkADCprog,
			 SyncInput => SyncInput,
          SW              => SW,
          ADC_Dres        => ADC_Dres,
          XFER1_N         => XFER1_N,
          OUFLOW1         => OUFLOW1,
  --      OUTEN_N         => OUTEN_N,
          DataIn          => DataIn,
          ADCCLK          => ADCCLK,
          CDSCLK1         => CDSCLK1,
          CDSCLK2         => CDSCLK2,
          SCLK            => SCLK,
          SLOAD_N         => SLOAD_N,
          SDATA           => SDATA,
          JP5IN           => JP5IN,
          DEBUG1          => DEBUG1,
          Dl              => Dl,
          D_latch         =>  D_latch,
  --      sample_weight   =>  sample_weight,
          ped_done        => ped_done,
          cds_done        => cds_done,
          accumulator     => accumulator,
          addsub_out      => addsub_out,
          add_sub         => add_sub,
          valid           => valid,
          cin             => cin
         );

ADC_D <= ADC_Dres(15 DOWNTO 0);
			
--U4: CompAD9826out
--port map(
--         GReset          => GReset,
--         SYSCLK          => SYSCLK,
--         ADC_D           => ADC_D,
--  --      addsub_out      => addsub_out,
--         accumulator     => accumulator,
--         ped_done        => ped_done,
--         valid           => valid,
--         cds_done        => cds_done
--         );
end ArchAD9826;